Learning to implement floating-point algorithms on FPGAs using high-level languages

R. Bruce, S. Marshall, M. Devlin, S. Vince

Research output: Contribution to conferencePaperpeer-review

139 Downloads (Pure)


FPGA-based reconfigurable computers can offer 10-1000 times speedup in many application domains over traditional microprocessor-based stored-program architectures. As a discipline, reconfigurable computing is in a period of change with little standards in place. It is becoming desirable to educate students in the principles of reconfigurable computing. This paper proposes that the abstraction benefits of high-level languages and floating-point arithmetic would shield students from the complexities of FPGA design and allow a syllabus with a greater focus on system-level aspects.
Original languageEnglish
Number of pages5
Publication statusPublished - 2006
EventThe 1st International Workshop on Reconfigurable Computing Education - Karlsruhe, Germany
Duration: 1 Mar 2006 → …


ConferenceThe 1st International Workshop on Reconfigurable Computing Education
Period1/03/06 → …


  • field-programmable gate arrays,
  • floating-point arithmetic
  • reconfigurable architectures,
  • electronics engineering education

Cite this