Learning to implement floating-point algorithms on FPGAs using high-level languages

R. Bruce; S. Marshall; M. Devlin; S. Vince

Learning to implement floating-point algorithms on FPGAs using high-level languages

R. Bruce, S. Marshall, M. Devlin, S. Vince

Electronic And Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

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Abstract

FPGA-based reconfigurable computers can offer 10-1000 times speedup in many application domains over traditional microprocessor-based stored-program architectures. As a discipline, reconfigurable computing is in a period of change with little standards in place. It is becoming desirable to educate students in the principles of reconfigurable computing. This paper proposes that the abstraction benefits of high-level languages and floating-point arithmetic would shield students from the complexities of FPGA design and allow a syllabus with a greater focus on system-level aspects.

Original language	English
Pages	1-5
Number of pages	5
Publication status	Published - 2006
Event	The 1st International Workshop on Reconfigurable Computing Education - Karlsruhe, Germany Duration: 1 Mar 2006 → …

Conference

Conference	The 1st International Workshop on Reconfigurable Computing Education
Country/Territory	Germany
City	Karlsruhe
Period	1/03/06 → …

Keywords

field-programmable gate arrays,
floating-point arithmetic
reconfigurable architectures,
electronics engineering education

Access to Document

311559Submitted manuscript, 92 KB

Cite this

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