Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH

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We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches in a novel hierarchy: efficient parallelism with Fast FIR Algorithm (FFA) structures, and efficient multiplierless FIR implementations with Hcub. The resource usage advantages (in both area and type) are compared with similar output from the traditional architecture, exemplified by vendor tools, as well as the Hcub-based filters without the FFA optimisation. Although these techniques are well studied individually in the literature, they have not enjoyed mainstream use as their structural complexity proves awkward to capture with traditional Hardware Description Languages (HDLs). This work continues a discussion of the use of functional programming techniques in hardware description, highlighting the benefits of having easily composable circuit generators.
Original languageEnglish
Title of host publication55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021
EditorsMichael B. Matthews
Place of PublicationNew York, NY
Number of pages8
ISBN (Electronic)9781665458283
ISBN (Print)9781665458290
Publication statusPublished - 4 Mar 2022
Event55th Asilomar Conference on Signals, Systems & Computers - Asilomar Grounds, Pacific Grove, United States
Duration: 31 Oct 20214 Nov 2021
Conference number: 55

Publication series

NameAsilomar Conference on Signals, Systems, and Computers
ISSN (Print)1058-6393
ISSN (Electronic)2576-2303


Conference55th Asilomar Conference on Signals, Systems & Computers
Country/TerritoryUnited States
CityPacific Grove
Internet address


  • digital signal processing
  • field programmable gate array
  • functional programming
  • multiplierless parallel filters

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